This invention relates to integrated circuits, and more particularly to differential buffer chips.
Memory modules are widely used in electronic systems such as personal computers (PCs). Various standards are used, such as those by the Joint Electronic Device Engineering Council (JEDEC). Some JEDEC standards use double-data-rate (DDR) dynamic-random-access memory (DRAM) chips on modules known as dual-inline-memory-modules (DIMMs). A newer DDR-2 standard is also being implemented. Differential input signals are used for faster signaling.
Very high-speed buffer chips are needed for interfacing with the DDR-2 DRAM's. Each data line, and perhaps some address or control signals are buffered. Bi-directional data lines can be supported by using two uni-directional data-buffer slices in parallel but in reverse directions.
FIG. 1 shows a bit-slice for a data buffer chip that interfaces with DDR-2 DRAMs. Data inputs D1, D2 are some of 25 or so data lines input to a buffer chip. Data input D1 is compared to a reference voltage Vref by differential buffer 12, then applied to the D-input of flip-flop 20. Likewise, data input D2 is compared to reference voltage Vref by differential buffer 14, then applied to the D-input of flip-flop 22. Vref is a reference voltage such as Vcc/2.
The Q1 output of inverting buffer 16 is a latched data bit that can be applied to one of the DDR-2 DRAM's data inputs. The Q2 output of inverting buffer 18 is another latched data bit that can be applied to another one of the DDR-2 DRAM's data inputs.
When SEL is low, mux 24 selects the upper input, causing Q1 to be driven from the latched D1 from flip-flop 20. When SEL is high, mux 24 selects its lower input, causing Q1 to be driven from the latched D2 from flip-flop 22. SEL can be a mode signal that is low to indicate 1:2 mode, but high to indicate 1:1 mode. In 1:1 mode, tow different outputs are generated from two different inputs, but in 1:2 mode two outputs are generated from the same (D2) input.
Clock buffer 26 receives a differential clock CK and CKB, and generates a clock edge to flip-flops 20, 22 when the differential clock signals cross-over. Reset signal RST can be applied to differential buffers 12, 14, clock buffer 26, and flip-flops 20, 22.
While such a data buffer is useful, an added clock-to-output propagation delay occurs for the Q1 data, which passes through mux 24 compared with the Q2 data that does not have to be delayed by mux 24. Mux 25 may include transmission gates and inverter buffers needed to re-generate signals that are reduced in strength by the effective resistance of the transmission gates.
Since tight delay times are specified by the JEDEC standard, the data-path delay may have to be reduced, such as by using a higher-speed buffer 16 or larger drive-current transistors in mux 24. However, increasing the speed of buffer 16 requires a large current, which increases power consumption. Since there can be as many as 25 bit slices such as shown in FIG. 1 in a buffer chip, a large overall power consumption can occur. Such large power consumptions are undesirable.
What is desired is a buffer chip with lower power dissipation. A faster clock-to-output data output path from the flip-flop is desirable without relying on large-current differential input buffers.